1. Field of the Invention
The present invention relates to a data transfer apparatus for transferring data, wherein a given portion of a memory is used as a buffer memory area.
2. Description of the Related Art
In conventional systems for transferring data between a plurality of devices (e.g. optical disk apparatus), data transfer between non-synchronous devices with different processing speeds is effected by various methods. For example, there is a method in which data transfer is started when access requests between both devices coincide. In a single buffer method, data of a predetermined size is temporarily transferred to a memory from a transmitter-side device, and thereafter a receiver-side device receives the data from the memory. In a double buffer method, two buffer memory systems are provided, and, after one of the buffer memory systems is filled with data, a receiver-side device starts a read access, during which time a transmitter-side device executes write access to the other buffer memory system.
In the method in which data transfer is started when access requests between both devices coincide, a bus is occupied while access requests are being awaited, resulting in a delay in access. Furthermore, if data widths are different between both devices, direct data transfer cannot be executed. In this case, data transfer is executed on the basis of the device with less data width. On the other hand, in the case of the single buffer method or double buffer method, the data transfer speed decreases because of a time for filling the buffer memory with data or overhead due to software control.
Jap. Pat. Appln. KOKAI Publication No. 58-201165 discloses a data rearrangement circuit, which is an example of a conventional double-buffer type circuit. This data rearrangement circuit is characterized by comprising two buffer memories having areas, the addresses of which can be optionally determined, and an address controller for controlling inputs and outputs independently with respect to addresses of the two buffer memories and designating output addresses in an optional order different from the order of input addresses. Specifically, the data rearrangement circuit includes two buffer memories. Data write is effected in one of the buffer memories, and data read is effected in the other buffer memory. For example, while data write is being performed in one buffer memory, data read is executed in the other buffer memory. Thereby, transfer speed is increased.
The double buffer method, however, has some drawbacks. For example, the operation of one device is suspended until one of the buffer memories is filled with data by the other device. In addition, since software control is executed when the buffer memory is switched, high-speed data transfer cannot be performed.